Ametek Lx Series II Programming Manual Instrukcja Użytkownika Pobierz pdf (Strona 160)

Programming Manual Lx \ Ls Series II

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7.6 Status Byte Register

This register summarizes the information from all other status groups as defined in the IEEE

488.2 Standard Digital Interface for Programmable Instrumentation. The bit configuration is shown

in Table 5-3.

Command Action

*STB? reads the data in the register but does not clear it (returns MSS in bit 6)

serial poll reads and clears the data in the register (returns RQS in bit 6)

The MSS Bit

This is a real-time (unlatched) summary of all Status Byte register bits that are enabled by the

Service Request Enable register. MSS is set whenever the AC source has one or more reasons

for requesting service. *STB? reads the MSS in bit position 6 of the response but does not clear

any of the bits in the Status Byte register.

The RQS Bit

The RQS bit is a latched version of the MSS bit. Whenever the AC source requests service, it

sets the SRQ interrupt line true and latches RQS into bit 6 of the Status Byte register. When the

controller does a serial poll, RQS is cleared inside the register and returned in bit position 6 of the

response. The remaining bits of the Status Byte register are not disturbed.

The MAV bit and Output Queue

The Output Queue is a first-in, first-out (FIFO) data register that stores AC source-to-controller

messages until the controller reads them. Whenever the queue holds one or more bytes, it sets

the MAV bit (bit 4) of the Status byte register.

1 2 ... 155 156 157 158 159 160 161 162 163 164 165 ... 241 242

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